Processor architectural evolution

Looking at the historical record, we can see that processor architectural evolution tends to develop as a repeating two-phase phenomenon—a stability phase being followed by a breakaway phase.

In the stability phase, we see concentration on implementation refinement while the architectures remain essentially unchanged.

• hardware architectures, embodying improvements such as the techniques

• compiler improvements, making it possible to better exploit architectural features

• instruction set extensions, but without breaking backwards binary compatibility; examples are the addition of multimedia capabilities, and the extension of addressing capabilities

The stability phase is one in which an equilibrium has been reached.

However, despite the equilibrium, in the background things are going steadily wrong, putting increasing pressure on extant architectures. Examples include the growing gulf between processor and memory speeds; the reduction in memory costs that make program size much less of an issue than before, and the increasing the integration capabilities of the technology. We can qualify such evolutions as being non-homotetic, since they destroy established equilibrium and lead eventually to a break; in other words, pressure is great enough to support a breakaway solution.

Such a breakaway solution is characterized also by a flock of new ideas and thinking, and of questioning of well-established “truths”. Two obvious examples are

• The appearance of RISC architectures

• The introduction of IA-64

This view of architectural evolution suggests it proceeds in a manner similar to an earthquake—for a long time, the deep movements are invisible except to those with the appropriate sensitive instrumentation; but eventually the tensions pass a critical threshold and the situation ruptures. A key difference between earthquakes and architecture evolution is that for architectures, the critical threshold keeps increasing, particularly in terms of the size of the necessary investment.

Source of Information :  Elsevier Server Architectures


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